Backends

This page lists the available backends.

Status matrix:

feature 6500 arm avr msp430 riscv stm8 x86_64
Samples build   yes yes yes yes   yes
Samples run   yes         yes
gdb remote client     yes   yes    
percentage complete 1% 70% 50% 20% 70% 1% 60%

6500

class ppci.arch.mos6500.Mos6500Arch(options=None)

arm

Arm machine specifics. The arm target has several options:

  • thumb: enable thumb mode, emits thumb code
class ppci.arch.arm.ArmArch(options=None)

Arm machine class.

avr

The is the avr backend.

class ppci.arch.avr.AvrArch(options=None)

Avr architecture description.

class ppci.arch.avr.registers.AvrRegister(name, num=None, aliases=())
class ppci.arch.avr.registers.AvrWordRegister(name, num=None, aliases=())

Register covering two 8 bit registers

digraph "classes_foo" { charset="utf-8" rankdir=BT "0" [label="{Adc|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "1" [label="{Add|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "2" [label="{Addw|rd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|render()\l}", shape="record"]; "3" [label="{And|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "4" [label="{Andw|rd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "5" [label="{Asr|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "6" [label="{AvrArch|assembler : BaseAssembler\lfp\lgdb_pc\lgdb_registers : tuple\lisa : Isa\lname : str\l|between_blocks()\ldetermine_arg_locations()\ldetermine_rv_location()\lepilogue()\lgen_copy_rv()\lgen_fill_arguments()\lget_runtime()\llitpool()\lmake_call()\lmove()\lprologue()\l}", shape="record"]; "7" [label="{AvrArithmaticToken|d : _p2\lop : _p2\lr : _p2\l|}", shape="record"]; "8" [label="{AvrInstruction|isa : Isa\l|}", shape="record"]; "9" [label="{AvrPointerRegister|\l|}", shape="record"]; "10" [label="{AvrProgramCounterRegister|bitsize : int\l|}", shape="record"]; "11" [label="{AvrPseudo16Register|\l|}", shape="record"]; "12" [label="{AvrRegCombo|hi\llo\l|}", shape="record"]; "13" [label="{AvrRegister|bitsize : int\lsyntaxi : tuple\l|}", shape="record"]; "14" [label="{AvrSpecialRegister|\l|}", shape="record"]; "15" [label="{AvrStackPointerRegister|bitsize : int\l|}", shape="record"]; "16" [label="{AvrStatusRegister|bitsize : int\l|}", shape="record"]; "17" [label="{AvrToken|b0 : _p2\lb1 : _p2\ln0 : _p2\ln1 : _p2\ln2 : _p2\ln3 : _p2\lw0 : _p2\l|}", shape="record"]; "18" [label="{AvrToken2|d : _p2\lop : _p2\lop2 : _p2\l|}", shape="record"]; "19" [label="{AvrToken3|a : _p2\ld : _p2\lop : _p2\l|}", shape="record"]; "20" [label="{AvrToken4|d : _p2\lk : _p2\lop : _p2\l|}", shape="record"]; "21" [label="{AvrToken5|b : _p2\lop : _p2\l|}", shape="record"]; "22" [label="{AvrWordRegister|bitsize : int\lhi\llo\lsyntaxi : tuple\l|}", shape="record"]; "23" [label="{Breq|lab : InstructionProperty\lpatterns : list\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "24" [label="{Brge|lab : InstructionProperty\lpatterns : list\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "25" [label="{Brlt|lab : InstructionProperty\lpatterns : list\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "26" [label="{Brne|lab : InstructionProperty\lpatterns : list\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "27" [label="{Call|lab : InstructionProperty\lpatterns : list\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "28" [label="{Cp|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "29" [label="{Cpc|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "30" [label="{Cpw|rd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "31" [label="{Dec|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "32" [label="{Eor|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "33" [label="{HighAvrRegister|syntaxi : tuple\l|}", shape="record"]; "34" [label="{HighAvrWordRegister|\l|}", shape="record"]; "35" [label="{Imm16Token|imm : _p2\l|}", shape="record"]; "36" [label="{In|na : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "37" [label="{Inc|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "38" [label="{Ld|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "39" [label="{LdPostInc|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "40" [label="{LdPreDec|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "41" [label="{Ldi|nk : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lreg_num\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "42" [label="{LdiHiAddr|lab : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lreg_num\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "43" [label="{LdiLoAddr|lab : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lreg_num\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "44" [label="{Ldiw|nk : InstructionProperty\lrd : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "45" [label="{LdiwAddr|lab : InstructionProperty\lrd : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "46" [label="{Lds|imm : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "47" [label="{LpmPostInc|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "48" [label="{Lsr|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "49" [label="{Mov|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "50" [label="{Movw|patterns : list\lrd : InstructionProperty\lrd_num\lrr : InstructionProperty\lrr_num\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "51" [label="{Nop|patterns : list\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "52" [label="{Or|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "53" [label="{Orw|rd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "54" [label="{Out|na : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "55" [label="{Pop|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "56" [label="{PseudoAvrInstruction|\l|}", shape="record"]; "57" [label="{Push|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "58" [label="{Ret|patterns : list\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "59" [label="{Reti|patterns : list\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "60" [label="{Rjmp|lab : InstructionProperty\lpatterns : list\lsyntax : Syntax\ltokens : list\l|relocations()\l}", shape="record"]; "61" [label="{Ror|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "62" [label="{Sbc|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "63" [label="{St|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "64" [label="{StPostInc|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "65" [label="{StPreDec|patterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "66" [label="{StWord|rd : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "67" [label="{Sts|imm : InstructionProperty\lpatterns : list\lrd : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "68" [label="{Sub|patterns : list\lrd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\ltokens : list\l|}", shape="record"]; "69" [label="{Subw|rd : InstructionProperty\lrr : InstructionProperty\lsyntax : Syntax\l|render()\l}", shape="record"]; "0" -> "8" [arrowhead="empty", arrowtail="none"]; "1" -> "8" [arrowhead="empty", arrowtail="none"]; "2" -> "56" [arrowhead="empty", arrowtail="none"]; "3" -> "8" [arrowhead="empty", arrowtail="none"]; "4" -> "56" [arrowhead="empty", arrowtail="none"]; "5" -> "8" [arrowhead="empty", arrowtail="none"]; "7" -> "17" [arrowhead="empty", arrowtail="none"]; "9" -> "34" [arrowhead="empty", arrowtail="none"]; "10" -> "14" [arrowhead="empty", arrowtail="none"]; "11" -> "12" [arrowhead="empty", arrowtail="none"]; "15" -> "14" [arrowhead="empty", arrowtail="none"]; "16" -> "14" [arrowhead="empty", arrowtail="none"]; "18" -> "17" [arrowhead="empty", arrowtail="none"]; "19" -> "17" [arrowhead="empty", arrowtail="none"]; "20" -> "17" [arrowhead="empty", arrowtail="none"]; "21" -> "17" [arrowhead="empty", arrowtail="none"]; "23" -> "8" [arrowhead="empty", arrowtail="none"]; "24" -> "8" [arrowhead="empty", arrowtail="none"]; "25" -> "8" [arrowhead="empty", arrowtail="none"]; "26" -> "8" [arrowhead="empty", arrowtail="none"]; "27" -> "8" [arrowhead="empty", arrowtail="none"]; "28" -> "8" [arrowhead="empty", arrowtail="none"]; "29" -> "8" [arrowhead="empty", arrowtail="none"]; "30" -> "56" [arrowhead="empty", arrowtail="none"]; "31" -> "8" [arrowhead="empty", arrowtail="none"]; "32" -> "8" [arrowhead="empty", arrowtail="none"]; "33" -> "13" [arrowhead="empty", arrowtail="none"]; "34" -> "22" [arrowhead="empty", arrowtail="none"]; "36" -> "8" [arrowhead="empty", arrowtail="none"]; "37" -> "8" [arrowhead="empty", arrowtail="none"]; "38" -> "8" [arrowhead="empty", arrowtail="none"]; "39" -> "8" [arrowhead="empty", arrowtail="none"]; "40" -> "8" [arrowhead="empty", arrowtail="none"]; "41" -> "8" [arrowhead="empty", arrowtail="none"]; "42" -> "8" [arrowhead="empty", arrowtail="none"]; "43" -> "8" [arrowhead="empty", arrowtail="none"]; "44" -> "56" [arrowhead="empty", arrowtail="none"]; "45" -> "56" [arrowhead="empty", arrowtail="none"]; "46" -> "8" [arrowhead="empty", arrowtail="none"]; "47" -> "8" [arrowhead="empty", arrowtail="none"]; "48" -> "8" [arrowhead="empty", arrowtail="none"]; "49" -> "8" [arrowhead="empty", arrowtail="none"]; "50" -> "8" [arrowhead="empty", arrowtail="none"]; "51" -> "8" [arrowhead="empty", arrowtail="none"]; "52" -> "8" [arrowhead="empty", arrowtail="none"]; "53" -> "56" [arrowhead="empty", arrowtail="none"]; "54" -> "8" [arrowhead="empty", arrowtail="none"]; "55" -> "8" [arrowhead="empty", arrowtail="none"]; "57" -> "8" [arrowhead="empty", arrowtail="none"]; "58" -> "8" [arrowhead="empty", arrowtail="none"]; "59" -> "8" [arrowhead="empty", arrowtail="none"]; "60" -> "8" [arrowhead="empty", arrowtail="none"]; "61" -> "8" [arrowhead="empty", arrowtail="none"]; "62" -> "8" [arrowhead="empty", arrowtail="none"]; "63" -> "8" [arrowhead="empty", arrowtail="none"]; "64" -> "8" [arrowhead="empty", arrowtail="none"]; "65" -> "8" [arrowhead="empty", arrowtail="none"]; "66" -> "56" [arrowhead="empty", arrowtail="none"]; "67" -> "8" [arrowhead="empty", arrowtail="none"]; "68" -> "8" [arrowhead="empty", arrowtail="none"]; "69" -> "56" [arrowhead="empty", arrowtail="none"]; "9" -> "6" [arrowhead="diamond", arrowtail="none", fontcolor="green", label="fp", style="solid"]; "10" -> "6" [arrowhead="diamond", arrowtail="none", fontcolor="green", label="gdb_pc", style="solid"]; }

See also:

https://gcc.gnu.org/wiki/avr-gcc

msp430

To flash the msp430 board, the following program can be used:

http://www.ti.com/tool/msp430-flasher

class ppci.arch.msp430.Msp430Arch(options=None)

Texas Instruments msp430 target architecture

risc-v

See also: http://riscv.org

Contributed by Michael.

class ppci.arch.riscv.RiscvArch(options=None)

stm8

STM8 is an 8-bit processor, see also: http://www.st.com/stm8

x86_64

For a good list of op codes, checkout:

http://ref.x86asm.net/coder64.html

For an online assembler, checkout:

https://defuse.ca/online-x86-assembler.htm

Linux

For a good list of linux system calls, refer:

http://blog.rchapman.org/post/36801038863/linux-system-call-table-for-x86-64

class ppci.arch.x86_64.X86_64Arch(options=None)

x86_64 architecture