risc-v

Backend for the risc-v platform. See also: https://riscv.org/

Testing

To test the riscv platform, the picorv32 project is used.

https://github.com/cliffordwolf/picorv32

Module

See also: http://riscv.org

Contributed by Michael.

class ppci.arch.riscv.RiscvArch(options=None)
between_blocks(frame)

Generate any instructions here if needed between two blocks

determine_arg_locations(arg_types)

Given a set of argument types, determine location for argument ABI: pass args in R12-R17 return values in R10

determine_rv_location(ret_type)

Determine the location of a return value of a function given the type of return value

gen_call(frame, label, args, rv)

Implement actual call and save / restore live registers

gen_epilogue(frame)

Return epilogue sequence for a frame. Adjust frame pointer and add constant pool

gen_function_enter(args)

Generate code to extract arguments from the proper locations

The default implementation tries to use registers and move instructions.

Parameters:args – an iterable of virtual registers in which the arguments must be placed.
gen_prologue(frame)

Returns prologue instruction sequence

get_runtime()

Implement compiler runtime functions

litpool(frame)

Generate instruction for the current literals

move(dst, src)

Generate a move from src to dst