Microblaze¶
The microblaze is a softcore architecture specified by xilinx. It is a 32 bit processor with 32 registers.
See also:
https://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf
Reference¶
Microblaze architecture.
Low level instruction class usage:
>>> from ppci.arch.microblaze import instructions, registers
>>> i = instructions.Add(registers.R4, registers.R5, registers.R6)
>>> str(i)
'add R4, R5, R6'
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class
ppci.arch.microblaze.MicroBlazeArch(options=None)¶ Microblaze architecture
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determine_arg_locations(arg_types)¶ Use registers R5-R10 to pass arguments
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determine_rv_location(ret_type)¶ Return values in R3-R4
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gen_call(frame, label, args, rv)¶ Generate proper calling sequence
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gen_epilogue(frame)¶ Return epilogue sequence for a frame.
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gen_function_enter(args)¶ Generate code to extract arguments from the proper locations
The default implementation tries to use registers and move instructions.
Parameters: args – an iterable of virtual registers in which the arguments must be placed.
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gen_litpool(frame)¶ Generate instructions for literals
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gen_prologue(frame)¶ Returns prologue instruction sequence.
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get_runtime()¶ Compiles the runtime support for microblaze.
It takes some c3 code.
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move(dst, src)¶ Generate a move from src to dst
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